User's Guide

Timer Registers

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5.3 Timer Period Registers (PRDHI and PRDLO)

The timer period registers (PRDLO and PRDHI) are 32-bit wide registers which can be used in conjunction

to form a single 64-bit period register (Figure 16) or separately as 32-bit period registers. These two

registers have the field shown in Figure 17 and described in Table 11 and are accessed via a separate

address.

In a 64-bit general-purpose timer mode and watchdog mode, all 64 period bits contain the number of timer

input clock cycles to count. This number controls the frequency of the timer output. In a 32-bit dual timer

mode, the period registers work as separate 32-bit registers.

These two registers are used in conjunction with the two counter-registers, CNTHI and CNTLO.

Figure 16. 64-Bit Timer Period Register

63 32 31 0

PRDHI PRDLO

R/W-0 R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Figure 17. Timer Period Registers (PRDHI and PRDLO)

31 0

PRD

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 11. Timer Period Registers (PRDHI and PRDLO) Field Descriptions

Bit Field Value Description

31-0 PRD 00000000h - Period register. This register contains the full timer period for a 32-bit timer configuration

FFFFFFFFh or half the timer period for a 64-bit timer configuration.

C6472/TCI648x 64-Bit Timer SPRU818B–December 2005–Revised September 2010

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