User guide

7.4 Configuring a PU
To configure a PU, you must do the following:
1. Define the starting addresses and sizes of protection regions, and enable them. To do this, write to coprocessor
register c6 in CP15, the system control coprocessor (see Setting protection region addresses and sizes, and
enabling each region).
2. Set the cacheable and bufferable attributes for each region. To do this, write to CP15 registers c2 and c3 (see
Setting region cacheable and bufferable flags).
3. Set access permissions for each region. To do this, write to CP15 register c5 (see Setting region access
permissions).
4. Enable the caches and enable the PU. To do this, write to CP15 register c1 (see Configuring core operation).
Note
The Pagetable model can do this for you if you are using ARMulator (see Models of caches and tightly coupled
memory and the ARMulator Basics chapter in Debug Target Guide
).
Note
Details of configuration vary from core to core. See the Technical Reference Manual for your particular core.
The following examples show the general methods of programming. They do not show correct details for every core.
7.4.1 Setting protection region addresses and sizes, and enabling each region
Example 7-1 sets the addresses and sizes of protection regions.
Note
Enabling the protection regions has no effect until you enable the PU.
Example 7-1 Setting protection regions
LDR r0,=0xFFFF801D ; define ROM with base address 0xFFFF8000, size 32KB, enabled
MCR p15,0,r0,c6,c1,0 ; apply this definition to data region 1
MCR p15,0,r0,c6,c1,1 ; apply the same definition to instruction region 1
LDR r0,=0xB0000039 ; define Peripherals with base address 0xB0000000, size 512MB, e
nabled
MCR p15,0,r0,c6,c2,0 ; apply this definition to data region 2
LDR r0,=0x4000001F ; define Data with base address 0x40000000, size 64KB, enabled
MCR p15,0,r0,c6,c3,0 ; apply this definition to data region 3
MOV r0,#0x1D ; define Code with base address 0x0, size 32KB, enabled
MCR p15,0,r0,c6,c4,0 ; apply this definition to data region 4
MCR p15,0,r0,c6,c4,1 ; apply the same definition to instruction region 4
Coprocessor register 6
Use c6 as the first coprocessor register to select the registers for region bases and sizes.
Selects the region using the second coprocessor register number, c1-c4 in the example.
The value in the ARM register, r0 in the example, contains:
• the base address, in bits [31:12]
• bits [11:6] must be zero
• the region size in bits [5:1] (see the Technical Reference Manual for your processor for details)
• setting bit [0] enables the region.
Opcode2
Opcode2 is only used for cores with separate data and instruction regions (see the Technical Reference Manual for
your processor for details).
Opcode2 must be zero if your processor does not support separate data and instruction regions. If it does support
them, 0 is for data regions, 1 for instruction regions.
7.4.2 Setting region cacheable and bufferable flags
Coprocessor register c2 of CP15 is the region cacheable flags register. Coprocessor register c3 of CP15 is the
region bufferable flags register. Example 7-2 sets the cacheable and bufferable flags for each data region.
If you set a region to be cacheable:
Caches and Tightly Coupled Memories
Copyright ?1999 2001 ARM Limited 7-5