Computer Hardware Algorithm Standard User's Guide
Table Of Contents
- Table of Contents
- Preface
- 1 Overview
- 2 General Programming Guidelines
- 3 Algorithm Component Model
- 3.1 Interfaces and Modules
- 3.1.1 External Identifiers
- 3.1.2 Naming Conventions
- 3.1.3 Module Initialization and Finalization
- 3.1.4 Module Instance Objects
- 3.1.5 Design-Time Object Creation
- 3.1.6 Run-Time Object Creation and Deletion
- 3.1.7 Module Configuration
- 3.1.8 Example Module
- 3.1.9 Multiple Interface Support
- 3.1.10 Interface Inheritance
- 3.1.11 Summary
- 3.2 Algorithms
- 3.3 Packaging
- 3.1 Interfaces and Modules
- 4 Algorithm Performance Characterization
- 5 DSP-Specific Guidelines
- 6 Use of the DMA Resource
- 6.1 Overview
- 6.2 Algorithm and Framework
- 6.3 Requirements for the Use of the DMA Resource
- 6.4 Logical Channel
- 6.5 Data Transfer Properties
- 6.6 Data Transfer Synchronization
- 6.7 Abstract Interface
- 6.8 Resource Characterization
- 6.9 Runtime APIs
- 6.10 Strong Ordering of DMA Transfer Requests
- 6.11 Submitting DMA Transfer Requests
- 6.12 Device Independent DMA Optimization Guideline
- 6.13 C6xxx Specific DMA Rules and Guidelines
- 6.14 C55x Specific DMA Rules and Guidelines
- 6.15 Inter-Algorithm Synchronization
- A Rules and Guidelines
- B Core Run-Time APIs
- C Bibliography
- D Glossary
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5.5.5 Register Conventions
TMS320C55x Rules and Guidelines
If the algorithm does not use B-bus, then the first column must be zero. If there is more than one block
that is accessed by the B-bus, then all the block numbers must be specified in the second column as
shown in the above example.
Example 2:
Any static-data that is accessed by the B-bus must be documented as per the Rule 37 as follows:
Data section names that are accessed by the
B-bus
.data
.coefwords
This way, the client will know which of the memory blocks and data-sections must be placed in on-chip
memory for the correct execution of the algorithm.
This section describes the rules and guidelines that apply to the use of the TMS320C55x on-chip
registers. Note that an algorithm must not access any register that is not described here.
The table below describes all of the registers that may be accessed by an algorithm. Please refer to
TMS320C55x Optimizing C/C++ Compiler User's Guide (SPRU281), Runtime Environment chapter, for
more details about the runtime conventions followed by the compiler.
Register Use Type
(X)AR0, (X)AR1, (X)AR2, (X)AR3, (X)AR4 Function arguments: data pointers (16- or 23-bit) or Scratch (local)
data values (16-bit)
(X)AR5, (X)AR6, (X)AR7 C compiler register variables Preserve (local)
AC0, AC1, AC2, AC3 16-bit, 32-bit and 40-bit data or 24-bit code pointers Scratch (local)
T0, T1 Function arguments: 16-bit data values Scratch (local)
T2, T3 C compiler expression registers Preserve (local)
SSP System Stack Pointer Preserve (local)
SP Stack Pointer Preserve (local)
ST0, ST1, ST2, ST3 Status registers Preserve (local)
IFR0, IMR0, IFR1, IMR1 Interrupt flag and mask register Read-only (global)
TRN0, TRN1 Transition registers Scratch (local)
BK03, BK47, BKC Circular Buffer Offset registers Scratch (local)
BRC0, BRC1 Block Repeat Counter registers Scratch (local)
RSA0, REA0, RSA1, REA1 Block repeat start and end address registers Scratch (local)
CDP Coefficient Data Pointer Scratch (local)
XDP Extended Data page pointer Scratch (local)
DP Memory data page start address Scratch (local)
PDP Peripheral Data page start address Scratch (local)
BOF01, BOF23, BOF45, BOF67, BOFC Circular buffer offset registers Scratch (local)
BIOS Data page pointer storage Read-only (global)
BRS0, BRS1 Block repeat save registers Scratch (local)
CSR Computed Single Repeat Scratch (local)
RPTC Repeat Single Counter Scratch (local)
XSP Extended data Stack pointer Preserve (local)
XCDP Extended coeff page pointer Scratch (local)
IVPD Interrupt vector pointer DSP Read-only (global)
IVPH Interrupt vector pointer host Read-only (global)
DSP-Specific Guidelines54 SPRU352G – June 2005 – Revised February 2007
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