Computer Hardware Algorithm Standard User's Guide
Table Of Contents
- Table of Contents
- Preface
- 1 Overview
- 2 General Programming Guidelines
- 3 Algorithm Component Model
- 3.1 Interfaces and Modules
- 3.1.1 External Identifiers
- 3.1.2 Naming Conventions
- 3.1.3 Module Initialization and Finalization
- 3.1.4 Module Instance Objects
- 3.1.5 Design-Time Object Creation
- 3.1.6 Run-Time Object Creation and Deletion
- 3.1.7 Module Configuration
- 3.1.8 Example Module
- 3.1.9 Multiple Interface Support
- 3.1.10 Interface Inheritance
- 3.1.11 Summary
- 3.2 Algorithms
- 3.3 Packaging
- 3.1 Interfaces and Modules
- 4 Algorithm Performance Characterization
- 5 DSP-Specific Guidelines
- 6 Use of the DMA Resource
- 6.1 Overview
- 6.2 Algorithm and Framework
- 6.3 Requirements for the Use of the DMA Resource
- 6.4 Logical Channel
- 6.5 Data Transfer Properties
- 6.6 Data Transfer Synchronization
- 6.7 Abstract Interface
- 6.8 Resource Characterization
- 6.9 Runtime APIs
- 6.10 Strong Ordering of DMA Transfer Requests
- 6.11 Submitting DMA Transfer Requests
- 6.12 Device Independent DMA Optimization Guideline
- 6.13 C6xxx Specific DMA Rules and Guidelines
- 6.14 C55x Specific DMA Rules and Guidelines
- 6.15 Inter-Algorithm Synchronization
- A Rules and Guidelines
- B Core Run-Time APIs
- C Bibliography
- D Glossary
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5.6.5 Status Registers
5.6.6 Interrupt Latency
5.7 TMS320C28x Rules and Guidelines
5.7.1 Data Models
TMS320C28x Rules and Guidelines
Register Use Type
AR6 - AR7 C compiler Register variables Yes
Accumulator Expression analysis/ return values from a C function Preserve(local)
P Resulting Product from a Multiply Scratch(local)
T Multiply and shift operand Scratch(local)
The C24xx contains two status registers: ST0 and ST1. Each status register is further divided into several
distinct fields. Although each field is often thought of as a separate register, it is not possible to access
these fields individually. In order to set one field it is necessary to set all fields in the same status register.
Therefore, it is necessary to treat the status registers with special care. For example, if any fields of a
status register is of type Preserve, the entire register must be treated as a Preserve register.
ST0 Field Name Use Type
ARP Auxiliary-register pointer Init (local)
OV Overflow flag Scratch(local)
OVM Overflow mode Init(local)
INTM Interrupt mode Preserve (global)
DP Data page Scratch(local)
ST1 Field Name Use Type
ARB Auxiliary-register pointer buffer Init (local)
CNF On-chip DARAM configuration Read-only(global)
TC Test/control flag Scratch(local)
SXM Sign-extension mode Scratch(local)
C Carry Scratch(local)
XF XF pin status Read-only (global)
PM Product shift mode Init (local)
The C24xx CPU has only one non-interruptible loop instruction, namely RPT. Once started, the RPT
instruction blocks interrupts until the entire number of repeats are completed. Thus, the length of these
loops can have a significant effect on the worst case interrupt latency of an algorithm.
This section presents the rules and guidelines that are specific to the TMS320C28x family of DSPs.
The TMS320C28x compiler supports a small memory model and a large memory model. These memory
models affect how data is placed in memory and accessed. The use of small memory model results in
code size that is slightly smaller than when using the large memory model. However this imposes certain
constraints on the memory placement of data. In the small memory model, all data in an application must
fit within the top 64K words. Since the algorithms are agnostic of where they are going to be instantiated,
all global and static data references should be implemented assuming the large memory model.
Rule 35
All TMS320C28xx algorithms must access all static and global data as far data; also, the algorithm
should be instantiable in a large memory model.
DSP-Specific Guidelines58 SPRU352G – June 2005 – Revised February 2007
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