Computer Hardware Algorithm Standard User's Guide

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V
X = 0ld
Y = new
VX
L2 cache External memory
Y
DMA
Cache line
6.14 C55x Specific DMA Rules and Guidelines
6.14.1 Supporting Packed/Burst Mode DMA Transfers
C55x Specific DMA Rules and Guidelines
DMA Rule 7 is a rule for the client application writer. For external memory buffers that are acquired using
DMA transfers, the corresponding cache entries must be invalidated to ensure that they are not cached.
For buffers that are modified using CPU accesses, the corresponding cache entries must first be written
back to external memory and then invalidated to ensure cache coherency.
It is also important that these buffers are allocated on a cache line boundary and be a multiple of cache
lines in size. As shown in Section 6.13.4 , if for some location x that is accessed by the DMA, there is other
data v sharing the same cache line, the entire cache line may be brought into the cache when v is
accessed. Location x would then end up in the cache, which violates the purpose of DMA Rule 6.
DMA Rule 8
For C6000 algorithms, all buffers residing in external memory involved in a DMA transfer should be
allocated on a cache line boundary and be a multiple of the cache line length in size.
DMA Rule 8 is added for algorithm writers who divide buffers supplied to them through their function
interface into smaller buffers, and then use these smaller buffers in DMA transfers. In this case, the
transfer must also occur on buffers aligned on a cache line boundary. Note that this does not mean the
transfer size needs to be a multiple of the cache line length in size. Instead, the "buffer" containing
memory locations involved in the transfer must be considered a single buffer; the algorithm must not
directly access part of the buffer as per DMA Rule 6.
DMA Rule 9
C6000 Algorithms should not use stack allocated buffers as the source or destination of any DMA
transfer.
DMA Rule 9 is necessary since buffers allocated on the stack are not aligned on cache line boundaries,
and there is no mechanism to force alignment. Furthermore, this rule is good practice, as it helps to
minimize an algorithm's stack size requirements.
Due to the performance requirements of certain C55x and OMAP platforms, DMA transfers must use
burst-enabled/packed transfer modes as much as possible. The basic problem is that if the source or
destination addresses are not aligned on a burst boundary, then the burst mode gets disabled by
hardware. DMA Guideline 4 is introduced to transparently assist ACPY2 library implementations on the
C55x platforms to operate in burst-enabled/packed mode.
DMA Guideline 4
To facilitate high performance, C55x algorithms should request DMA transfers with source and
destinations aligned on 32-bit byte addresses.
Use of the DMA Resource70 SPRU352G – June 2005 – Revised February 2007
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