Stereo System User Manual

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4.16.2 RTI/Digital Watchdog Registers Description(s)
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A
followed by 0xA35C in two separate writes) must be continually written to the key register before the
watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to
provide an added measure of robustness against a software failure. If the application fails and ceases to
write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the
application.
Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires;
however, Capture 0 is still available for use by the application as well as the remaining RTI resources.
Table 4-36 is a list of the RTI registers.
Table 4-36. RTI Registers
BYTE ADDRESS REGISTER NAME DESCRIPTION
Device-Level Configuration Registers Controlling RTI
0x4000 0014 CFGRTI Selects the sources for the RTI input captures from among the six McASP DMA event.
RTI Internal Registers
0x4200 0000 RTIGCTRL Global Control Register. Starts / stops the counters.
0x4200 0004 Reserved Reserved bit.
0x4200 0008 RTICAPCTRL Capture Control. Controls the capture source for the counters.
0x4200 000C RTICOMPCTRL Compare Control. Controls the source for the compare registers.
0x4200 0010 RTIFRC0 Free-Running Counter 0. Current value of free-running counter 0.
0x4200 0014 RTIUC0 Up-Counter 0. Current value of prescale counter 0.
0x4200 0018 RTICPUC0 Compare Up-Counter 0. Compare value compared with prescale counter 0.
0x4200 0020 RTICAFRC0 Capture Free-Running Counter 0. Current value of free-running counter 0 on external
event.
0x4200 0024 RTICAUC0 Capture Up-Counter 0. Current value of prescale counter 0 on external event.
0x4200 0030 RTIFRC1 Free-Running Counter 1. Current value of free-running counter 1.
0x4200 0034 RTIUC1 Up-Counter 1. Current value of prescale counter 1.
0x4200 0038 RTICPUC1 Compare Up-Counter 1. Compare value compared with prescale counter 1.
0x4200 0040 RTICAFRC1 Capture Free-Running Counter 1. Current value of free-running counter 1 on external
event.
0x4200 0044 RTICAUC1 Capture Up-Counter 1. Current value of prescale counter 1 on external event.
0x4200 0050 RTICOMP0 Compare 0. Compare value to be compared with the counters.
0x4200 0054 RTIUDCP0 Update Compare 0. Value to be added to the compare register 0 value on compare
match.
0x4200 0058 RTICOMP1 Compare 1. Compare value to be compared with the counters.
0x4200 005C RTIUDCP1 Update Compare 1. Value to be added to the compare register 1 value on compare
match.
0x4200 0060 RTICOMP2 Compare 2. Compare value to be compared with the counters.
0x4200 0064 RTIUDCP2 Update Compare 2. Value to be added to the compare register 2 value on compare
match.
0x4200 0068 RTICOMP3 Compare 3. Compare value to be compared with the counters.
0x4200 006C RTIUDCP3 Update Compare 3. Value to be added to the compare register 3 value on compare
match.
0x4200 0070 Reserved Reserved bit.
0x4200 0074 Reserved Reserved bit.
0x4200 0080 RTISETINT Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a
read-modify-write operation.
0x4200 0084 RTICLEARINT Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to
do a read-modify-write operation.
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