User manual

Contents
Preface .............................................................................................................................. 11
1 Introduction ............................................................................................................. 13
1.1 Overview..................................................................................................................... 14
1.2 ARM Subsystem in TMS320DM646x DMSoC ......................................................................... 14
2 ARM Subsystem Overview ......................................................................................... 15
2.1 Purpose of the ARM Subsystem ......................................................................................... 16
2.2 Components of the ARM Subsystem .................................................................................... 16
2.3 References .................................................................................................................. 17
3 ARM Core ................................................................................................................ 19
3.1 Introduction .................................................................................................................. 20
3.2 Operating States/Modes ................................................................................................... 21
3.3 Processor Status Registers ............................................................................................... 21
3.4 Exceptions and Exception Vectors ....................................................................................... 22
3.5 The 16-BIS/32-BIS Concept .............................................................................................. 23
3.5.1 16-BIS/32-BIS Advantages ...................................................................................... 23
3.6 Co-Processor 15 (CP15) .................................................................................................. 24
3.6.1 Addresses in an ARM926EJ-S System ........................................................................ 24
3.6.2 Memory Management Unit (MMU) .............................................................................. 24
3.6.3 Caches and Write Buffer ........................................................................................ 25
3.7 Tightly-Coupled Memory .................................................................................................. 26
4 System Memory ....................................................................................................... 29
4.1 Memory Map ................................................................................................................ 30
4.1.1 ARM Internal Memories .......................................................................................... 30
4.1.2 External Memories ................................................................................................ 30
4.1.3 DSP Memories ..................................................................................................... 30
4.1.4 Peripherals ......................................................................................................... 30
4.2 Memory Interfaces Overview ............................................................................................. 31
4.2.1 DDR2 Memory Controller ........................................................................................ 31
4.2.2 External Memory Interface ....................................................................................... 31
5 PLL Controller .......................................................................................................... 35
5.1 PLL Module ................................................................................................................. 36
5.2 PLL1 Control ................................................................................................................ 38
5.2.1 Device Clock Generation ......................................................................................... 39
5.2.2 Steps for Changing PLL1/Core Domain Frequency .......................................................... 39
5.3 PLL2 Control ................................................................................................................ 41
5.3.1 Device Clock Generation ......................................................................................... 42
5.3.2 Steps for Changing PLL2 Frequency ........................................................................... 42
5.4 PLL Controller Register Map .............................................................................................. 45
5.4.1 Peripheral ID Register (PID) ..................................................................................... 46
5.4.2 Reset Type Status Register (RSTYPE) ........................................................................ 46
SPRUEP9A – May 2008 Contents 3
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