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7.4.2 DSP Sleep Modes ................................................................................................. 82
7.5 I/O Management ............................................................................................................ 83
7.5.1 3.3 V I/O Power-Down ............................................................................................ 83
7.6 USB Phy Power Down ..................................................................................................... 83
8 ARM Interrupt Controller (AINTC) ............................................................................... 85
8.1 Introduction .................................................................................................................. 86
8.2 Interrupt Mapping ........................................................................................................... 86
8.3 AINTC Methodology ....................................................................................................... 88
8.3.1 Interrupt Mapping .................................................................................................. 88
8.3.2 Interrupt Prioritization ............................................................................................. 89
8.3.3 Vector Table Entry Address Generation ....................................................................... 89
8.3.4 Clearing Interrupts................................................................................................. 90
8.3.5 Enabling and Disabling Interrupts ............................................................................... 90
8.4 AINTC Registers ........................................................................................................... 91
8.4.1 Fast Interrupt Request Status Register 0 (FIQ0) .............................................................. 92
8.4.2 Fast Interrupt Request Status Register 1 (FIQ1) .............................................................. 92
8.4.3 Interrupt Request Status Register 0 (IRQ0) ................................................................... 93
8.4.4 Interrupt Request Status Register 1 (IRQ1) ................................................................... 93
8.4.5 Fast Interrupt Request Entry Address Register (FIQENTRY) ............................................... 94
8.4.6 Interrupt Request Entry Address Register (IRQENTRY) ..................................................... 94
8.4.7 Interrupt Enable Register 0 (EINT0) ............................................................................ 95
8.4.8 Interrupt Enable Register 1 (EINT1) ............................................................................ 95
8.4.9 Interrupt Operation Control Register (INTCTL) ................................................................ 96
8.4.10 Interrupt Entry Table Base Address Register (EABASE) ................................................... 97
8.4.11 Interrupt Priority Register 0 (INTPRI0) ........................................................................ 98
8.4.12 Interrupt Priority Register 1 (INTPRI1) ........................................................................ 98
8.4.13 Interrupt Priority Register 2 (INTPRI2) ........................................................................ 99
8.4.14 Interrupt Priority Register 3 (INTPRI3) ........................................................................ 99
8.4.15 Interrupt Priority Register 4 (INTPRI4) ....................................................................... 100
8.4.16 Interrupt Priority Register 5 (INTPRI5) ....................................................................... 100
8.4.17 Interrupt Priority Register 6 (INTPRI6) ....................................................................... 101
8.4.18 Interrupt Priority Register 7 (INTPRI7) ....................................................................... 101
9 System Control Module ........................................................................................... 103
9.1 Overview of the System Control Module .............................................................................. 104
9.2 Device Identification ...................................................................................................... 104
9.3 Device Configuration ..................................................................................................... 105
9.3.1 Pin Multiplexing Control ........................................................................................ 105
9.3.2 Device Boot Configuration Status ............................................................................. 105
9.3.3 Device Boot Process Status .................................................................................... 105
9.4 ARM-DSP Integration .................................................................................................... 105
9.4.1 ARM-DSP Interrupt Control and Status ....................................................................... 105
9.4.2 DSP Boot Address Control and Status ....................................................................... 105
9.5 Power Management ...................................................................................................... 106
9.5.1 V
DD
3.3 V I/O Power-Down Control ............................................................................ 106
9.6 Special Peripheral Status and Control ................................................................................. 106
9.6.1 Universal Serial Bus (USB) Interface Control ................................................................ 106
9.6.2 Host Port Interface (HPI) Control .............................................................................. 106
9.6.3 Video Clock Control and Disable .............................................................................. 106
SPRUEP9A – May 2008 Contents 5
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