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8.3 AINTC Methodology
IRQ/FIQ
map
00
0-63
INTn
INTPRIn[2:1]
IRQn
INT
enable
FIQn
EINTn
Prioritizer
IRQn
EABASE
IRQzTo ARM Entry
address
generator
IRQENTRY
Entry
address
generator
FIQENTRY
Prioritizer
FIQn
FIQz To ARM
8.3.1 Interrupt Mapping
AINTC Methodology www.ti.com
AINTC methodology is illustrated in Figure 8-1 and described below.
• When an interrupt occurs, the status is reflected in either the FIQn or the IRQn registers, depending
upon the interrupt type selected.
• Interrupts are enabled or disabled (masked) by setting the EINTn register.
Note: Even if an interrupt is masked, the status interrupt is still reflected in the FIQn and the IRQn
registers.
• When an interrupt from any interrupt channel occurs (for which interrupt is enabled), an IRQ or FIQ
interrupt generates to the ARM926EJ core (depending on whether the interrupt channel is mapped to
IRQ or FIQ interrupt). The ARM then branches to the IRQ or FIQ interrupt routine.
• The AINTC generates the entry address of the pending interrupt with the highest priority and stores the
entry address in the FIQENTRY or the IRQENTRY register, depending on whether the interrupt is
mapped to IRQ or FIQ interrupt. The IRQ or FIQ ISR can then read the entry address and its branch to
the ISR of the interrupt.
Figure 8-1. AINTC Functional Diagram
Each event input is mapped to either the ARM IRQ or to the FIQ interrupt based on the priority level
selected in the INTPRIn register. Events with a priority of 0 or 1 are designated as FIQs; events with
priorities of 2-7 are designated as IRQs. The appropriate IRQ / FIQ registers capture interrupt events.
Each event causes an IRQ or FIQ to generate only if the corresponding EINT bit enables it. The EINT bit
enables or disables the event regardless of whether it is mapped to IRQ or to FIQ. The IRQ/FIQ register
always captures each event, regardless of whether the interrupt is actually enabled.
88 ARM Interrupt Controller (AINTC) SPRUEP9A – May 2008
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