User manual

7.3 Clock Management
7.3.1 Module Clock ON/OFF
7.3.2 Module Clock Frequency Scaling
7.3.3 PLL Bypass and Power Down
7.4 ARM and DSP Sleep Mode Management
7.4.1 ARM Wait-For-Interrupt Sleep Mode
www.ti.com Clock Management
The module clock on/off feature allows software to disable clocks to module individually, in order to reduce
the module's active power consumption to 0. The DM646x DMSoC is designed in full static CMOS; thus,
when a module clock stops, the module's state is preserved. When the clock is restarted, the module
resumes operating from the stopping point.
Note: Stopping clocks to a module only affects active power consumption, it does not affect
leakage power consumption.
If a module's clock(s) is stopped while the configuration bus or the EDMA bus is accessing it, the access
may not occur, and could potentially lock-up the bus. Ensure that all of the transactions to the module are
finished prior to stopping the clocks.
The power and sleep controller (PSC) controls module clock gating. The procedure to turn module clocks
on/off is described in Chapter 6 .
Module clock frequency is scalable by programming the PLL's multiply and divide parameters. Reducing
the clock frequency reduces the active switching power consumption linearly with frequency. It has no
impact on leakage power consumption.
Chapter 5 describes how to program the PLL frequency and the frequency constraints.
The PLLs can be bypassed in the DM646x DMSoC. Bypassing the PLLs sends the PLL reference clock to
the post dividers of the PLLC instead of to the PLL VCO output. The PLL reference clock is typically at
27 MHZ; therefore, this bypass mode can be used to reduce the core and module clock frequencies to
very low maintenance levels without using the PLL during periods of very low system activity.
Furthermore, the PLL can be powered down in bypass mode to save additional active power.
Chapter 5 describes PLL bypass and PLL power down details.
The ARM module cannot have its clock gated in the PSC module. However, the ARM includes a special
sleep mode called “wait-for-interrupt”. When the wait-for-interrupt mode is enabled, the clock to the CPU
core is shut off and the ARM9 is completely inactive and only resumes operation after receiving an
interrupt. This mode does not affect leakage consumption.
You can enable the wait-for-interrupt mode via the CP15 register #7 using the following instruction:
• mcr p15, #0, rd, c7, c0, #4
The following sequence exemplifies how to enter wait-for-interrupt mode:
• Enable any interrupt (for example, an external interrupt).
• Enable wait-for-interrupt mode using the following CP15 instruction:
– mcr p15, #0, rd, c7, c0, #4
SPRUEP9A – May 2008 Power Management 81
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