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6.5.2 Interrupt Register Bits

6.5.3 Interrupt Handling

PSC Interrupts

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The PSC interrupt enable bits are the EMUIHBIE bit and the EMURSTIE bit in the module control n

Note: To interrupt the ARM, the ARM’s power and sleep controller interrupt (PSCINT) must also be

enabled in the ARM interrupt controller (AINTC). See Chapter 8 for more information on the

ARM interrupt controller.

The PSC interrupt status bits are the M[ n] bits in the module error pending register n (MERRPR n), and the

EMUIHB bit and the EMURST bit in the module status n register (MDSTAT n). The status bits in

MERRPR0 and MERRPR1 are read by software to determine which module has generated an emulation

interrupt, and then software can read the corresponding status bits in MDSTAT n to determine which event

caused the interrupt.

The PSC interrupt clear bits are the M[ n] bits in the module error clear register n (MERRCR n).

The PSC interrupt evaluation bit is the ALLEV bit in the interrupt evaluation register (INTEVAL). When set,

this bit forces the PSC interrupt logic to re-evaluate event status. If any events are still active (if any status

bits are set) when the ALLEV bit in INTEVAL is set to 1, the PSCINT is reasserted to the ARM interrupt

controller. Set the ALLEV bit in INTEVAL before exiting your PSCINT interrupt service routine to ensure

that you do not miss any PSC interrupts while the ARM interrupts are globally disabled.

See Section 6.6 for complete descriptions of all PSC registers.

Handle the PSC interrupts as described in the following procedure:

Enable the interrupt.

1. Set the EMUIHBIE bit and the EMURSTIE bit in the module control n register (MDCTL n) to enable the

interrupt events that you want.

2. Enable the ARM power and sleep controller interrupt (PSCINT) in the ARM interrupt controller. To

interrupt the ARM, PSCINT must be enabled in the ARM interrupt controller. See Chapter 8 for more

information.

The ARM enters the interrupt service routine (ISR) when it receives the interrupt.

1. Read the M[ n] bit in the module error pending register n (MERRPR n) to determine the source of the

interrupt(s).

2. For each active event that you want to service:

• Read the event status bits in the module status n register (MDSTAT n), depending on the status

bits read in the previous step to determine the event that caused the interrupt.

• Service the interrupt as required by your application.

• Write a 1 to the M[ n] bit in the module error clear register n (MERRCR n) to clear corresponding

status.

• Set the ALLEV bit in the interrupt evaluation register (INTEVAL). Setting this bit reasserts the

PSCINT to the ARM interrupt controller, if there are still any active interrupt events.

68 Power and Sleep Controller (PSC) SPRUEP9A – May 2008

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